Announcement
Synergy Quantum India Private Limited issued a press release in New Delhi on June 18, 2026 announcing a new portfolio of quantum‑safe silicon IP cores designed specifically for RISC‑V‑based system‑on‑chip (SoC) designs. The announcement positions the IP as a means for semiconductor companies, processor developers and equipment manufacturers to embed post‑quantum cryptographic capabilities directly into ASICs, FPGAs and embedded platforms.
Portfolio Features
The portfolio incorporates a range of post‑quantum algorithms, including ML‑KEM for key establishment, ML‑DSA for digital signatures, SLH‑DSA and LMS hash‑signature schemes, HQC for algorithmic diversity, as well as SHA‑3, Keccak and Ascon for hashing and authenticated encryption. It also provides shared number‑theoretic transform (NTT) acceleration, secure and measured boot, firmware‑signature verification, hardware‑enforced anti‑rollback, PUF‑derived device identity, DICE‑style attestation, protected key derivation and sealing, and hybrid classical‑post‑quantum operation. Implementations can be scaled from low‑power, compact blocks for IoT devices to high‑throughput accelerators for telecom, networking, data‑centre and security‑appliance applications.
Configurability and Architecture
The IP cores combine programmable RISC‑V control logic with dedicated cryptographic datapaths, allowing security policies and protocol handling to be managed via software while intensive cryptographic operations execute in isolated hardware. The architecture supports industry‑standard SoC interconnects and processor‑extension interfaces, enabling integration without a full redesign of the host platform. Crypto‑agility is built in through reusable arithmetic engines, shared NTT and Keccak components, and programmable security control, facilitating algorithm updates and hardware‑enforced anti‑rollback mechanisms for long‑lifecycle products.
Target Markets and Applications
Synergy Quantum targets a broad ecosystem that includes RISC‑V processor and SoC developers, semiconductor manufacturers, design houses, foundries, FPGA developers, defence and aerospace electronics firms, telecom and network‑equipment makers, industrial and operational‑technology vendors, automotive and autonomous‑system developers, IoT and embedded‑device manufacturers, as well as cloud, data‑centre and security‑appliance providers. The cores can be embedded in secure processors, network controllers, communications equipment, gateways, firewalls, hardware‑security platforms, industrial controllers, satellite systems and other long‑lifecycle connected devices.
Complementary Offering
The new RISC‑V quantum‑safe IP portfolio complements Synergy Quantum’s previously announced SynQ Silicon Trust Suite, which provides a system‑level framework for secure boot, protected key custody, device identity, signing, attestation and security‑policy enforcement. Together, the offerings deliver a vertically integrated solution spanning quantum‑safe cryptographic hardware, RISC‑V integration, hardware‑rooted identity, secure boot, protected key lifecycle management and device attestation.
Quote
"RISC‑V gives semiconductor developers the flexibility to build processors and systems around their own requirements. Quantum‑safe security must become part of that flexibility and must be available as a native silicon capability rather than an afterthought added at the software layer," said Jay Oberai, Founder of Synergy Quantum.
Strategic Implications
The press release highlights that ownership and control of cryptographic silicon IP are increasingly important for governments, defence organisations, critical‑infrastructure operators and semiconductor manufacturers. By providing configurable, auditable RISC‑V‑based quantum‑safe IP, Synergy Quantum aims to reduce reliance on external cryptographic components and enable sovereign control over algorithm selection, security policies and cryptographic lifecycle management.